The present invention relates to technology of manufacturing a semiconductor device, in particular, to the technology which is effective when applied to the manufacturing of a semiconductor device that mounts a plurality of semiconductor chips, chip parts, etc.
For the purposes of downsizing a mounting substrate (motherboard) that mounts semiconductor packages, chip parts (resistor, capacitor, inductor, etc.), etc., and of increasing the speed of a semiconductor system, an MCM (Multi Chip Module) type semiconductor device that mixedly mounts various kinds of semiconductor chip (microcomputer chip, memory chip, etc.) and chip parts in one semiconductor device is being developed.
As a configuration of such an MCM type semiconductor device, mention is made of, for example, that of a POP (Package On Package) type semiconductor device in which a plurality of wiring substrates over which semiconductor chips or chip parts are mounted is prepared and on one of the wiring substrates, the other wiring substrate is stacked, as shown in Japanese Patent Laid-Open No. 2007-123454 (Patent Document 1).
Further, as a configuration of another POP type semiconductor device, mention is made of, for example, that in which a wiring substrate (first substrate 10) in the lower tier is electrically coupled to a wiring substrate (second substrate 20) in the upper tier via a ball-shaped electrode and over the wiring substrate in the upper tier, another semiconductor package is mounted, as shown in FIG. 2(D) in Japanese Patent Laid-Open No. 2008-288490 (Patent Document 2).
Furthermore, as a configuration of another POP type semiconductor device, mention is made of, for example, that in which electrodes (bump 118) are formed in advance over a wiring substrate (first wiring layer 101) in the lower tier and a wiring substrate (second wiring layer 104) in the upper tier, respectively, and these wiring substrates are joined to each other, as shown in FIG. 10(h) in Japanese Patent Laid-Open No. 2008-300498 (Patent Document 3).